Resource Utilization - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

The hardware resources are listed in Table 164. This is for the demonstration as configured by default (two cfB76Engine engines) achieving a 300 MHz clock rate.

Table 164 Hardware resources for single kernel with two parallel cfB76Engine engines.
Engines BRAM DSP Register LUT Latency clock period(ns)
b76_kernel 374 496 77741 65491 334 3.333