This API is a front-end submodule of SVPWM function. A complete SVPWM function is composed of two components: SVPWM_DUTY and PWM_GEN. This API is the SVPWM_DUTY. It is a fully optimized implementation through the Xilinx HLS design methodology. It can produce the normalized duty ratios of the three-phase outputs. It has configurable parameters via AXI-Lite entries, include phase_shift, dclink_src, pwm_freq and dead_cycles, etc.