Overview - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

This API can been seen as the back-end submodule of SVPWM function. A complete SVPWM function is composed of two components: SVPWM_DUTY and PWM_GEN. This API is the PWM_GEN. It is a fully optimized implementation through the Xilinx HLS design methodology. It can produce the bitstreams to control the switches on/off on every branch of the bridges. The input are the normalized duty ratios from the upstream SVPWM_DUTY. The outputs are 3 sets waveforms including the high, low and sync sets for a, b, and c signals.