Executable Usage - 2023.2 English

Vitis Libraries

Release Date
2023.2 English
  • Work Directory(Step 1)

The steps for library download and environment setup can be found in l2_vitis_graph. For getting the design,

cd L2/benchmarks/strongly_connected_component
  • Build kernel(Step 2)

Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.

make run TARGET=hw PLATFORM=xilinx_u250_xdma_201830_2
  • Run kernel(Step 3)

To get the benchmark results, please run the following command.

./build_dir.hw.xilinx_u250_xdma_201830_2/host.exe -xclbin build_dir.hw.xilinx_u250_xdma_201830_2/scc_kernel.xclbin -o data/test_offset.csr -c data/test_column.csr -g data/test_golden.mtx

Strongly Connected Component Input Arguments:

Usage: host.exe -[-xclbin -o -c -g]
       -xclbin     strongly connected component binary
       -o          offset file of input graph in CSR format
       -c          edge file of input graph in CSR format
       -g          golden reference file for validatation

Note: Default arguments are set in Makefile, you can use other Datasets listed in the table.

  • Example output(Step 4)
---------------------SCC Test----------------
Found Platform
Platform Name: Xilinx
Found Device=xilinx_u250_xdma_201830_2
INFO: Importing build_dir.hw.xilinx_u250_xdma_201830_2/scc_kernel.xclbi
Loading: 'build_dir.hw.xilinx_u250_xdma_201830_2/scc_kernel.xclbin'
kernel has been created
kernel start------
Input: numVertex=13, numEdges=19
kernel end------
Execution time 53.929ms
Write DDR Execution time 0.115905ms
Kernel Execution time 53.37ms
Read DDR Execution time 0.039641ms
Total Execution time 53.5255ms
HW components:6
The number of components:6
Check Passed.