Benchmark - 2023.2 English

Vitis Libraries
Release Date
2023-12-20
Version
2023.2 English

The performance is shown in the table below.

Table 129 Table 2 Comparison between CPU and FPGA (iteration=30)
Datasets Vertex Edges CPU time FPGA time Speedup
coPapersCiteseer 434102 16036720 0.26 0.309 84.14%
coPapersDBLP 540486 15245729 0.31 0.317 97.79%
hollywood 1139905 57515616 1.78 1.21 147.11%
as-Skitter 1694616 11094209 0.74 0.344 215.12%
cit-Patents 3774768 16518948 2.07 0.584 354.45%

Note

  1. Maximal independent set CPU time benchmarking is running on Intel(R) Xeon(R) CPU E5-2667 v3 @ 3.20GHz, cache(2048 KB), cores(31)
  2. time unit: ms.
  3. This mis implementation focus on single-kernel-level design and focusing on mid-scale dataset processing. As showed in table, with the increasing of the graph vertex number, the FPGA show increasingly advantage over CPU offloading.
  4. The performance is tested under config of “set_property -dict [list CONFIG.ECC_EN {false} CONFIG.ECC_SCRUB_EN {false}] [get_bd_cells hmss_0]”