Implemention - 2023.2 English

Vitis Libraries
Release Date
2023-12-20
Version
2023.2 English

The input matrix should ensure that the following conditions hold:

  1. No duplicate edges
  2. compressed sparse column/row (CSC/CSR) format

The algorithm implemention is shown as the figure below:

Figure 1 : convert CSC CSR architecture on FPGA

Figure 1 Convert CSC CSR architecture on FPGA

As we can see from the figure:

  1. firstly call the Module calculate degree to generate the transfer offset array.
  2. by using the input offset and indice arrays and also the calculated new offset array, generate the new indice array