Implemention - 2023.2 English

Vitis Libraries
Release Date
2023-12-20
Version
2023.2 English

The input matrix should ensure that the following conditions hold:

  1. No duplicate edges
  2. compressed sparse column/row (CSC/CSR) format

The algorithm implemention is shown as the figure below:

Figure 1 : calculate degree architecture on FPGA

Figure 1 PageRank calculate degree architecture on FPGA

As we can see from the figure:

  1. Module calculate degree: first get the vertex node’s outdegree and keep them in one DDR buffer.