SSR_FFT_NO_SCALE - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

When the scaling_mode constant in the parameter structure is set to SSR_FFT_NO_SCALE, the bit growth is allowed in every stage and the output grows unbounded by log2(R) in every stage. This setting can be useful when high precision is required. However, if the output bit width grows beyond 27 bits, the multiplication may not map to only DSPs, but also start using FPGA fabric logic in combination. This may reduce the clock speed and increase resource utilization.