Executable Usage - 2023.2 English

Vitis Libraries

Release Date
2023.2 English
  • Work Directory(Step 1)

The steps for library download and environment setup can be found in l2_vitis_database. For getting the design,

cd L1/benchmarks/hash_multi_join
  • Build kernel(Step 2)

Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.

make run TARGET=hw PLATFORM=xilinx_u280_xdma_201920_3
  • Run kernel(Step 3)

To get the benchmark results, please run the following command.

./build_dir.hw.xilinx_u280_xdma_201920_3/test_join.exe -xclbin build_dir.hw.xilinx_u280_xdma_201920_3/hash_multi_join.xclbin

Hash Multi-Join Input Arguments:

Usage: test_join.exe -xclbin
       -xclbin:      the kernel name

Note: Default arguments are set in Makefile, you can use other platforms to build and run.

  • Example output(Step 4)
------------- Hash-Join Test ----------------
Data integer width is 32.
Host map buffer has been allocated.
Lineitem 6001215 rows
Orders 227597rows
Lineitem table has been read from disk
Orders table has been read from disk
INFO: CPU ref matched 5389889 rows, sum = 2543814013792128
Found Platform
Platform Name: Xilinx
Selected Device xilinx_u280_xdma_201920_3
INFO: Importing build_dir.hw.xilinx_u280_xdma_201920_3/hash_multi_join.xclbin
Loading: 'build_dir.hw.xilinx_u280_xdma_201920_3/hash_multi_join.xclbin'
Kernel has been created
DDR buffers have been mapped/copy-and-mapped
FPGA result 0: 254381401379.2128
Golden result: 254381401379.2128
FPGA execution time of 1 runs: 84605 usec
Average execution per run: 84605 usec
INFO: kernel 0: execution time 76899 usec
Test Pass