Executable Usage - 2023.2 English

Vitis Libraries

Release Date
2023.2 English
  • Work Directory(Step 1)

The steps for library download and environment setup can be found in l2_vitis_database. For getting the design,

cd L1/benchmarks/hash_join_v2
  • Build kernel(Step 2)

Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.

make run TARGET=hw PLATFORM=xilinx_u280_xdma_201920_3
  • Run kernel(Step 3)

To get the benchmark results, please run the following command.

./build_dir.hw.xilinx_u280_xdma_201920_3/test_join.exe -xclbin build_dir.hw.xilinx_u280_xdma_201920_3/hash_join.xclbin

Hash Join V2 Input Arguments:

Usage: test_join.exe -xclbin
       -xclbin:      the kernel name

Note: Default arguments are set in Makefile, you can use other platforms to build and run.

  • Example output(Step 4)
------------- Hash-Join Test ----------------
Data integer width is 32.
Host map buffer has been allocated.
Lineitem 6001215 rows
Orders 227597rows
Lineitem table has been read from disk
Orders table has been read from disk
INFO: CPU ref matched 13659906 rows, sum = 6446182945969752
Found Platform
Platform Name: Xilinx
Selected Device xilinx_u280_xdma_201920_3
INFO: Importing build_dir.hw.xilinx_u280_xdma_201920_3/hash_join_v2.xclbin
Loading: 'build_dir.hw.xilinx_u280_xdma_201920_3/hash_join_v2.xclbin'
Kernel has been created
DDR buffers have been mapped/copy-and-mapped
FPGA result 0: 644618294596.9752
Golden result 0: 644618294596.9752
FPGA execution time of 1 runs: 63985 usec
Average execution per run: 63985 usec
INFO: kernel 0: execution time 55945 usec