Executable Usage - 2023.2 English

Vitis Libraries

Release Date
2023.2 English
  • Work Directory(Step 1)

The steps for library download and environment setup can be found in l2_vitis_data_analytics. For getting the design,

cd L2/benchmarks/classification/svm
  • Build kernel(Step 2)

Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.

make run TARGET=hw PLATFORM=xilinx_u250_gen3x16_xdma_3_1_202020_1
  • Run kernel(Step 3)

To get the benchmark results, please run the following command.

./build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/test_svm.exe -xclbin build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/svm_4krnl.xclbin -in ./ml_datasets/1000.csv -trn 999 -ten 100 -fn 64 -itrn 1 -bn 10

Support vector machine Input Arguments:

Usage: test_svm.exe -xclbin <xclbin_name> -in <input_data> -trn <TBD> -ten <TBD> -fn <TBD> -itrn <TBD> -bn <TBD >
       -xclbin:      the kernel name
       -in    :      input data
       -trn   :      TBD
       -ten   :      TBD
       -fn    :      TBD
       -itrn  :      TBD
       -bn    :      TBD

Note: Default arguments are set in Makefile, you can use other platforms to build and run.

  • Example output(Step 4)
--------- SVM Test ---------
Found Platform
Platform Name: Xilinx
Selected Device xilinx_u250_gen3x16_xdma_shell_3_1
INFO: Importing build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/svm_4krnl.xclbin
rows num:999
cols num:65
creating buf_data
creating buf_weight
DDR buffers have been mapped/copy-and-mapped
Kernel execution timn: 0.23ms
Decision Tree FPGA times:1 ms
kernel0:0: -0.00900901
kernel0:1: -0.0510511
kernel0:2: -0.033033
kernel3:62: -0.013013
kernel3:63: -0.047047