Feature Tutorials - 2023.2 English

Vitis Tutorials: Vitis Platform Creation (XD101)

Document ID: XD101
Release Date: 2023-12-26
Version: 2023.2 English

Tutorial	Device Family	Board	Platform Type	IDE Flow	Design Target
Incorporating Stream Interfaces	Generic, but using Versal AI Core as example	VCK190	Flat	Vivado Vitis IDE	Highlights: Adding custom IP into the platform hardware. Using AXI Stream IP in platform and kernel.
PetaLinux Building and System Customization	Zynq UltraScale+ MPSoC and Versal AI Core	ZCU104 and VCK190	Flat	Vivado Vitis IDE	Highlights: Customize the software components with PetaLinux.
Hardware Design Fast Iteration with Vitis Export to Vivado	Versal AI Core	VCK190	Block Design Container	Vivado Vitis IDE	Highlights: Skip creating the platform before v++ linking. Using Vivado to do design implementation and timing closure. Fast iteration for hardware design.
Hardware Design Validation	Versal AI Core	VCK190	Flat & Block Design Container	Vivado Vitis IDE	Highlights: Link kernel with XSA directly. Validation against hardware platform interfaces. Validate the hardware design with bare-metal application.

XSA: Vivado exported archive file that contains hardware information required for Vitis and PetaLinux
DFX: Dynamic Function eXchange
SOM: System-on-Modules
DTB: Device Tree Binary
DTBO: Device Tree Binary Overlay