The base design is a simple example of an APU subsystem with a register-based PL design to allow the user to check if a PL subsystem was re-programmed or reset without the user actively issuing a reset. In the pl_alive module, there is register that uses the Power On Reset (POR) mechanism of the Versal device to set a register to a high value on initial power up. This register is reset to a low value by the APU writing to a register and should stay low as long as the PL is operational. There is also a pulse input to the module that acts as a heartbeat to the PL indicating that the APU is also alive. The pl_alive module takes this pulse signal and toggles an output port on the module which can be read by the APU to see that the PL is responding to the pulse signal. There is also an AXI GPIO module that has a fixed unique value for the software to read, which is used to detect the design version in the PL.