Primitive: RXTX_BITSLICE for bidirectional I/O using Native Mode
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BITSLICE
- Families: UltraScale, UltraScale+
Introduction
In native mode, the RXTX_BITSLICE performs both functions of an RX_BITSLICE and TX_BITSLICE for bidirectional I/O.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
D<7:0> | Input | 8 | Data from device logic. |
DATAIN | Input | 1 | Input signal from IOBUF. |
FIFO_EMPTY | Output | 1 | FIFO empty flag for the FIFO of this bit. |
FIFO_RD_CLK | Input | 1 | FIFO read clock for the FIFO of this bit. |
FIFO_RD_EN | Input | 1 | FIFO read enable for the FIFO of this bit. |
FIFO_WRCLK_OUT | Output | 1 | FIFO source synchronous write clock out to the device logic. Only valid for RX_BITSLICE 0. Currently not supported, do not connect. |
O | Output | 1 | Serialized output going to output buffer. |
Q<7:0> | Output | 8 | Registered output data from FIFO. |
RX_BIT_CTRL_IN<39:0> | Input | 40 | RX Input bus from BITSLICE_CONTROL. |
RX_BIT_CTRL_OUT<39:0> | Output | 40 | RX Output bus to BITSLICE_CONTROL. |
RX_CE | Input | 1 | Clock enable for RXTX_BITSLICE IDELAY register clock. |
RX_CLK | Input | 1 | RX Clock used to sample LOAD, CE, INC. |
RX_CNTVALUEIN<8:0> | Input | 9 | RX Counter value from internal device logic for tap value to be loaded dynamically. |
RX_CNTVALUEOUT<8:0> | Output | 9 | RX Counter value from internal device logic for tap value to be loaded dynamically. |
RX_EN_VTC | Input | 1 | RX Enable to keep stable delay over VT when set to HIGH. VT compensation disabled when set to LOW. |
RX_INC | Input | 1 | RX Increment the current delay tap setting. |
RX_LOAD | Input | 1 | RX Load the CNTVALUEIN tap setting. |
RX_RST | Input | 1 | RX Asynchronous assert, synchronous deassert for RXTX_BITSLICE ISERDES. |
RX_RST_DLY | Input | 1 | RX Reset the internal DELAY value to DELAY_VALUE. |
T | Input | 1 | Legacy T byte input from device logic. |
TBYTE_IN | Input | 1 | Byte group 3-state input from TX_BITSLICE_TRI. |
T_OUT | Output | 1 | Byte group 3-state output. |
TX_BIT_CTRL_IN<39:0> | Input | 40 | TX Input bus from BITSLICE_CONTROL. |
TX_BIT_CTRL_OUT<39:0> | Output | 40 | Output bus to BITSLICE_CONTROL for TX. |
TX_CE | Input | 1 | Clock enable for RXTX_BITSLICE ODELAY register clock. |
TX_CLK | Input | 1 | TX Clock used to sample LOAD, CE, INC. |
TX_CNTVALUEIN<8:0> | Input | 9 | TX Counter value from internal device logic for tap value to be loaded dynamically. |
TX_CNTVALUEOUT<8:0> | Output | 9 | TX Counter value to going the internal device logic for monitoring tap value. |
TX_EN_VTC | Input | 1 | TX Enable to keep stable delay over VT when set to HIGH. VT compensation disabled when set to LOW. |
TX_INC | Input | 1 | TX Increment the current delay tap setting. |
TX_LOAD | Input | 1 | TX Load the CNTVALUEIN tap setting. |
TX_RST | Input | 1 | TX Asynchronous assert, synchronous deassert for RXTX_BITSLICE OSERDES. |
TX_RST_DLY | Input | 1 | TX Reset the internal DELAY value to DELAY_VALUE. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
ENABLE_PRE_EMPHASIS | STRING | "FALSE", "TRUE" | "FALSE" | Used in conjunction with IOB to Enable the pre-emphasis. |
FIFO_SYNC_MODE | STRING | "FALSE", "TRUE" | "FALSE" | Attribute defining the relationship between FIFO_WRCLK_OUT and FIFO_RD_CLK. Always set this attribute to FALSE. TRUE is reserved for later use. |
INIT | BINARY | 1'b1, 1'b0 | 1'b1 | Defines initial O value |
IS_RX_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the clock RX_CLK pin is active-High or active-Low. |
IS_RX_RST_DLY_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the reset RX_RST_DLY pin is active-High or active-Low. |
IS_RX_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the reset RX_RST pin is active-High or active-Low. |
IS_TX_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the clock TX_CLK pin is active-High or active-Low. |
IS_TX_RST_DLY_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the reset TX_RST_DLY pin is active-High or active-Low. |
IS_TX_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the reset TX_RST pin is active-High or active-Low. |
RX_DATA_TYPE | STRING | "DATA", "CLOCK", "DATA_AND_CLOCK", "SERIAL" | "DATA" | Defines whether the RX input pin is carrying a clock signal, a data signal, or clock signal that is also used as data. |
RX_DATA_WIDTH | DECIMAL | 8, 4 | 8 | Defines the width of the serial-to-parallel converter. Legal data widths are 4 and 8. |
RX_DELAY_FORMAT | STRING | "TIME", "COUNT" | "TIME" | Sets the units of DELAY_VALUE of the RXTX_BITSLICE IDELAY. Use TIME when DELAY_TYPE is FIXED. Use COUNT when DELAY_TYPE is VARIABLE or VAR_LOAD.
|
RX_DELAY_TYPE | STRING | "FIXED", "VARIABLE", "VAR_LOAD" | "FIXED" | Sets the type of RX tap delay line.
|
RX_DELAY_VALUE | DECIMAL | 0 to 1250 | 0 | Specifies the RX fixed delay in ps when using FIXED DELAY_TYPE. Specifies RX value upon reset when using VARIABLE or VAR_LOAD. |
RX_REFCLK_FREQUENCY | 1 significant digit FLOAT | 200.0 to 2667.0 | 300.0 | Specification of the RX reference clock frequency in MHz. |
RX_UPDATE_MODE | STRING | "ASYNC", "MANUAL", "SYNC" | "ASYNC" |
|
SIM_DEVICE | STRING | "7SERIES", "ULTRASCALE" | "ULTRASCALE" | Set the device version for simulation functionality. |
TBYTE_CTL | STRING | "TBYTE_IN", "T" | "TBYTE_IN" | Select between T and TBYTE_IN inputs in OSERDES mode only |
TX_DATA_WIDTH | DECIMAL | 8, 4 | 8 | Defines the parallel data input width. Legal values are 4 and 8. |
TX_DELAY_FORMAT | STRING | "TIME", "COUNT" | "TIME" | Sets the units of DELAY_VALUE of the RXTX_BITSLICE ODELAY. Use TIME when DELAY_TYPE is FIXED. Use COUNT when DELAY_TYPE is VARIABLE or VAR_LOAD.
|
TX_DELAY_TYPE | STRING | "FIXED", "VARIABLE", "VAR_LOAD" | "FIXED" | Sets the type of TX tap delay line.
|
TX_DELAY_VALUE | DECIMAL | 0 to 1250 | 0 | Specifies the TX fixed delay in ps when using FIXED DELAY_TYPE. Specifies TX value upon reset when using VARIABLE or VAR_LOAD. |
TX_OUTPUT_PHASE_90 | STRING | "FALSE", "TRUE" | "FALSE" | Delays the output phase by 90-degrees. |
TX_REFCLK_FREQUENCY | 1 significant digit FLOAT | 200.0 to 2667.0 | 300.0 | Specification of the TX reference clock frequency in MHz. |
TX_UPDATE_MODE | STRING | "ASYNC", "MANUAL", "SYNC" | "ASYNC" |
|
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RXTX_BITSLICE: RXTX_BITSLICE for bidirectional I/O using Native Mode
-- UltraScale
-- Xilinx HDL Language Template, version 2023.1
RXTX_BITSLICE_inst : RXTX_BITSLICE
generic map (
ENABLE_PRE_EMPHASIS => "FALSE", -- Enable the pre-emphasis
FIFO_SYNC_MODE => "FALSE", -- Always set to FALSE. TRUE is reserved for later use.
INIT => '1', -- Defines initial O value
IS_RX_CLK_INVERTED => '0', -- Optional inversion for RX_CLK
IS_RX_RST_DLY_INVERTED => '0', -- Optional inversion for RX_RST_DLY
IS_RX_RST_INVERTED => '0', -- Optional inversion for RX_RST
IS_TX_CLK_INVERTED => '0', -- Optional inversion for TX_CLK
IS_TX_RST_DLY_INVERTED => '0', -- Optional inversion for TX_RST_DLY
IS_TX_RST_INVERTED => '0', -- Optional inversion for TX_RST
RX_DATA_TYPE => "DATA", -- Defines what the RX input pin is carrying (CLOCK, DATA,
-- DATA_AND_CLOCK, SERIAL)
RX_DATA_WIDTH => 8, -- Defines the width of the serial-to-parallel converter (4-8)
RX_DELAY_FORMAT => "TIME", -- Units of the RX DELAY_VALUE (COUNT, TIME)
RX_DELAY_TYPE => "FIXED", -- Set the type of RX tap delay line (FIXED, VARIABLE, VAR_LOAD)
RX_DELAY_VALUE => 0, -- RX Input delay value setting in ps
RX_REFCLK_FREQUENCY => 300.0, -- Specification of the RX reference clock frequency in MHz
-- (200.0-2667.0)
RX_UPDATE_MODE => "ASYNC", -- Determines when updates to the RX delay will take effect (ASYNC,
-- MANUAL, SYNC)
SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
-- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
TBYTE_CTL => "TBYTE_IN", -- Select between T and TBYTE_IN inputs
TX_DATA_WIDTH => 8, -- Parallel data input width (4-8)
TX_DELAY_FORMAT => "TIME", -- Units of the TX DELAY_VALUE (COUNT, TIME)
TX_DELAY_TYPE => "FIXED", -- Set the type of TX tap delay line (FIXED, VARIABLE, VAR_LOAD)
TX_DELAY_VALUE => 0, -- TX Input delay value setting in ps
TX_OUTPUT_PHASE_90 => "FALSE", -- Delays the output phase by 90-degrees
TX_REFCLK_FREQUENCY => 300.0, -- Specification of the TX reference clock frequency in MHz
-- (200.0-2667.0)
TX_UPDATE_MODE => "ASYNC" -- Determines when updates to the delay will take effect (ASYNC, MANUAL,
-- SYNC)
)
port map (
FIFO_EMPTY => FIFO_EMPTY, -- 1-bit output: FIFO empty flag
FIFO_WRCLK_OUT => FIFO_WRCLK_OUT, -- 1-bit output: FIFO source synchronous write clock out to the
-- device logic (currently unsupported, do not connect)
O => O, -- 1-bit output: Serialized output going to output buffer
Q => Q, -- 8-bit output: Registered output data from FIFO
RX_BIT_CTRL_OUT => RX_BIT_CTRL_OUT, -- 40-bit output: RX Output bus to BITSLICE_CONTROL
RX_CNTVALUEOUT => RX_CNTVALUEOUT, -- 9-bit output: RX Counter value from device logic
TX_BIT_CTRL_OUT => TX_BIT_CTRL_OUT, -- 40-bit output: Output bus to BITSLICE_CONTROL for TX
TX_CNTVALUEOUT => TX_CNTVALUEOUT, -- 9-bit output: TX Counter value to device logic
T_OUT => T_OUT, -- 1-bit output: Byte group 3-state output
D => D, -- 8-bit input: Data from device logic
DATAIN => DATAIN, -- 1-bit input: Input signal from IOBUF
FIFO_RD_CLK => FIFO_RD_CLK, -- 1-bit input: FIFO read clock
FIFO_RD_EN => FIFO_RD_EN, -- 1-bit input: FIFO read enable
RX_BIT_CTRL_IN => RX_BIT_CTRL_IN, -- 40-bit input: RX Input bus from BITSLICE_CONTROL
RX_CE => RX_CE, -- 1-bit input: Clock enable for IDELAY
RX_CLK => RX_CLK, -- 1-bit input: RX Clock used to sample LOAD, CE, INC
RX_CNTVALUEIN => RX_CNTVALUEIN, -- 9-bit input: RX Counter value from device logic
RX_EN_VTC => RX_EN_VTC, -- 1-bit input: RX Enable to keep stable delay over VT
RX_INC => RX_INC, -- 1-bit input: RX Increment the current delay tap setting
RX_LOAD => RX_LOAD, -- 1-bit input: RX Load the CNTVALUEIN tap setting
RX_RST => RX_RST, -- 1-bit input: RX Asynchronous assert, synchronous deassert for
-- RXTX_BITSLICE ISERDES
RX_RST_DLY => RX_RST_DLY, -- 1-bit input: RX Reset the internal DELAY value to DELAY_VALUE
T => T, -- 1-bit input: Legacy T byte input from device logic
TBYTE_IN => TBYTE_IN, -- 1-bit input: Byte group 3-state input from TX_BITSLICE_TRI
TX_BIT_CTRL_IN => TX_BIT_CTRL_IN, -- 40-bit input: TX Input bus from BITSLICE_CONTROL
TX_CE => TX_CE, -- 1-bit input: Clock enable for ODELAY
TX_CLK => TX_CLK, -- 1-bit input: TX Clock used to sample LOAD, CE, INC
TX_CNTVALUEIN => TX_CNTVALUEIN, -- 9-bit input: TX Counter value from device logic
TX_EN_VTC => TX_EN_VTC, -- 1-bit input: TX Enable to keep stable delay over VT
TX_INC => TX_INC, -- 1-bit input: TX Increment the current delay tap setting
TX_LOAD => TX_LOAD, -- 1-bit input: TX Load the CNTVALUEIN tap setting
TX_RST => TX_RST, -- 1-bit input: TX Asynchronous assert, synchronous deassert for
-- RXTX_BITSLICE OSERDES
TX_RST_DLY => TX_RST_DLY -- 1-bit input: TX Reset the internal DELAY value to DELAY_VALUE
);
-- End of RXTX_BITSLICE_inst instantiation
Verilog Instantiation Template
// RXTX_BITSLICE: RXTX_BITSLICE for bidirectional I/O using Native Mode
// UltraScale
// Xilinx HDL Language Template, version 2023.1
RXTX_BITSLICE #(
.ENABLE_PRE_EMPHASIS("FALSE"), // Enable the pre-emphasis
.FIFO_SYNC_MODE("FALSE"), // Always set to FALSE. TRUE is reserved for later use.
.INIT(1'b1), // Defines initial O value
.IS_RX_CLK_INVERTED(1'b0), // Optional inversion for RX_CLK
.IS_RX_RST_DLY_INVERTED(1'b0), // Optional inversion for RX_RST_DLY
.IS_RX_RST_INVERTED(1'b0), // Optional inversion for RX_RST
.IS_TX_CLK_INVERTED(1'b0), // Optional inversion for TX_CLK
.IS_TX_RST_DLY_INVERTED(1'b0), // Optional inversion for TX_RST_DLY
.IS_TX_RST_INVERTED(1'b0), // Optional inversion for TX_RST
.RX_DATA_TYPE("DATA"), // Defines what the RX input pin is carrying (CLOCK, DATA,
// DATA_AND_CLOCK, SERIAL)
.RX_DATA_WIDTH(8), // Defines the width of the serial-to-parallel converter (4-8)
.RX_DELAY_FORMAT("TIME"), // Units of the RX DELAY_VALUE (COUNT, TIME)
.RX_DELAY_TYPE("FIXED"), // Set the type of RX tap delay line (FIXED, VARIABLE, VAR_LOAD)
.RX_DELAY_VALUE(0), // RX Input delay value setting in ps
.RX_REFCLK_FREQUENCY(300.0), // Specification of the RX reference clock frequency in MHz
// (200.0-2667.0)
.RX_UPDATE_MODE("ASYNC"), // Determines when updates to the RX delay will take effect (ASYNC,
// MANUAL, SYNC)
.SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
// ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
.TBYTE_CTL("TBYTE_IN"), // Select between T and TBYTE_IN inputs
.TX_DATA_WIDTH(8), // Parallel data input width (4-8)
.TX_DELAY_FORMAT("TIME"), // Units of the TX DELAY_VALUE (COUNT, TIME)
.TX_DELAY_TYPE("FIXED"), // Set the type of TX tap delay line (FIXED, VARIABLE, VAR_LOAD)
.TX_DELAY_VALUE(0), // TX Input delay value setting in ps
.TX_OUTPUT_PHASE_90("FALSE"), // Delays the output phase by 90-degrees
.TX_REFCLK_FREQUENCY(300.0), // Specification of the TX reference clock frequency in MHz
// (200.0-2667.0)
.TX_UPDATE_MODE("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL,
// SYNC)
)
RXTX_BITSLICE_inst (
.FIFO_EMPTY(FIFO_EMPTY), // 1-bit output: FIFO empty flag
.FIFO_WRCLK_OUT(FIFO_WRCLK_OUT), // 1-bit output: FIFO source synchronous write clock out to the device
// logic (currently unsupported, do not connect)
.O(O), // 1-bit output: Serialized output going to output buffer
.Q(Q), // 8-bit output: Registered output data from FIFO
.RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT), // 40-bit output: RX Output bus to BITSLICE_CONTROL
.RX_CNTVALUEOUT(RX_CNTVALUEOUT), // 9-bit output: RX Counter value from device logic
.TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL for TX
.TX_CNTVALUEOUT(TX_CNTVALUEOUT), // 9-bit output: TX Counter value to device logic
.T_OUT(T_OUT), // 1-bit output: Byte group 3-state output
.D(D), // 8-bit input: Data from device logic
.DATAIN(DATAIN), // 1-bit input: Input signal from IOBUF
.FIFO_RD_CLK(FIFO_RD_CLK), // 1-bit input: FIFO read clock
.FIFO_RD_EN(FIFO_RD_EN), // 1-bit input: FIFO read enable
.RX_BIT_CTRL_IN(RX_BIT_CTRL_IN), // 40-bit input: RX Input bus from BITSLICE_CONTROL
.RX_CE(RX_CE), // 1-bit input: Clock enable for IDELAY
.RX_CLK(RX_CLK), // 1-bit input: RX Clock used to sample LOAD, CE, INC
.RX_CNTVALUEIN(RX_CNTVALUEIN), // 9-bit input: RX Counter value from device logic
.RX_EN_VTC(RX_EN_VTC), // 1-bit input: RX Enable to keep stable delay over VT
.RX_INC(RX_INC), // 1-bit input: RX Increment the current delay tap setting
.RX_LOAD(RX_LOAD), // 1-bit input: RX Load the CNTVALUEIN tap setting
.RX_RST(RX_RST), // 1-bit input: RX Asynchronous assert, synchronous deassert for
// RXTX_BITSLICE ISERDES
.RX_RST_DLY(RX_RST_DLY), // 1-bit input: RX Reset the internal DELAY value to DELAY_VALUE
.T(T), // 1-bit input: Legacy T byte input from device logic
.TBYTE_IN(TBYTE_IN), // 1-bit input: Byte group 3-state input from TX_BITSLICE_TRI
.TX_BIT_CTRL_IN(TX_BIT_CTRL_IN), // 40-bit input: TX Input bus from BITSLICE_CONTROL
.TX_CE(TX_CE), // 1-bit input: Clock enable for ODELAY
.TX_CLK(TX_CLK), // 1-bit input: TX Clock used to sample LOAD, CE, INC
.TX_CNTVALUEIN(TX_CNTVALUEIN), // 9-bit input: TX Counter value from device logic
.TX_EN_VTC(TX_EN_VTC), // 1-bit input: TX Enable to keep stable delay over VT
.TX_INC(TX_INC), // 1-bit input: TX Increment the current delay tap setting
.TX_LOAD(TX_LOAD), // 1-bit input: TX Load the CNTVALUEIN tap setting
.TX_RST(TX_RST), // 1-bit input: TX Asynchronous assert, synchronous deassert for
// RXTX_BITSLICE OSERDES
.TX_RST_DLY(TX_RST_DLY) // 1-bit input: TX Reset the internal DELAY value to DELAY_VALUE
);
// End of RXTX_BITSLICE_inst instantiation
Related Information
- UltraScale Architecture SelectIO Resources User Guide (UG571)