Primitive: Analog Auxiliary SYSMON Input Buffer
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
- Families: UltraScale, UltraScale+
Introduction
This design element is an input buffer used to connect the auxiliary analog inputs to the SYSMONE1 component. When using the VAUXP/VAUXN pins of the SYSMONE1 component, this buffer allows for a proper connection to the top-level port in the design.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Connect this pin to a top-level port in the design. |
| O | Output | 1 | Connect this pin to the VAUXP or VAUXN port of a SYSMONE1 component. |
Design Entry Method
| Instantiation | Yes |
| Inference | Yes |
| IP and IP Integrator Catalog | Recommended |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUF_ANALOG: Analog Auxiliary SYSMON Input Buffer
-- UltraScale
-- Xilinx HDL Language Template, version 2023.1
IBUF_ANALOG_inst : IBUF_ANALOG
port map (
O => O, -- 1-bit output: Connect to a VAUXP/VAUXN port of the SYSMONE1
I => I -- 1-bit input: Connect to a top-level design port
);
-- End of IBUF_ANALOG_inst instantiation
Verilog Instantiation Template
// IBUF_ANALOG: Analog Auxiliary SYSMON Input Buffer
// UltraScale
// Xilinx HDL Language Template, version 2023.1
IBUF_ANALOG IBUF_ANALOG_inst (
.O(O), // 1-bit output: Connect to a VAUXP/VAUXN port of the SYSMONE1
.I(I) // 1-bit input: Connect to a top-level design port
);
// End of IBUF_ANALOG_inst instantiation
Related Information
- UltraScale Architecture System Monitor User Guide (UG580)