BUFGCTRL - 2023.1 English

Primitive: General Clock Control Buffer

PRIMITIVE_GROUP: CLOCK
PRIMITIVE_SUBGROUP: MUX
Families: UltraScale, UltraScale+

Introduction

BUFGCTRL primitive is a general clock buffer that is designed as a synchronous/asynchronous "glitch-free" 2:1 multiplexer with two clock inputs. If clock multiplexing is not necessary, you should use a BUFG or BUFGCE component.

Port Descriptions

Port	Direction	Width	Function
CE0	Input	1	Clock enable input for the I0 clock input. A setup/hold time must be guaranteed when you are using the CE0 pin to enable this input. Failure to meet this requirement could result in a clock glitch.
CE1	Input	1	Clock enable input for the I1 clock input. A setup/hold time must be guaranteed when you are using the CE1 pin to enable this input. Failure to meet this requirement could result in a clock glitch.
IGNORE0	Input	1	Clock ignore input for I0 input. Asserting the IGNORE pin prevents the BUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.
IGNORE1	Input	1	Clock ignore input for I1 input. Asserting the IGNORE pin prevents the BUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.
I0	Input	1	Primary clock input into the BUFGCTRL enabled by the CE0 input and selected by the S0 input.
I1	Input	1	Secondary clock input into the BUFGCTRL enabled by the CE1 input and selected by the S1 input.
O	Output	1	Clock output
S0	Input	1	Clock select input for I0. The S pins represent the clock select pin for each clock input. When using the S pin as input select, there is a setup/hold time requirement. Unlike CE pins, failure to meet this requirement will not result in a clock glitch. However, it can cause the output clock to appear one clock cycle later.
S1	Input	1	Clock select input for I1. The S pins represent the clock select pin for each clock input. When using the S pin as input select, there is a setup/hold time requirement. Unlike CE pins, failure to meet this requirement will not result in a clock glitch. However, it can cause the output clock to appear one clock cycle later.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
INIT_OUT	DECIMAL	0, 1	0	Initializes the BUFGCTRL output to the specified value after configuration.
PRESELECT_I0	BOOLEAN	FALSE, TRUE	FALSE	If TRUE, BUFGCTRL output uses I0 input after configuration.
PRESELECT_I1	BOOLEAN	FALSE, TRUE	FALSE	If TRUE, BUFGCTRL output uses I1 input after configuration.
SIM_DEVICE	STRING	"7SERIES", "ULTRASCALE"	"ULTRASCALE"	Set the device version
Programmable Inversion Attributes: Specifies whether or not to use the optional inversion on specific pins for this component to change the active polarity of the pin function. When set to 1, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_CE0_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the CE0 pin of this component.
IS_CE1_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the CE1 pin of this component.
IS_IGNORE0_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the IGNORE0 pin of this component.
IS_IGNORE1_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the IGNORE1 pin of this component.
IS_I0_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the I0 pin of this component.
IS_I1_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the I1 pin of this component.
IS_S0_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the S0 pin of this component.
IS_S1_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the S1 pin of this component.

Note: Both PRESELECT attributes might not be TRUE at the same time.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- BUFGCTRL: General Clock Control Buffer
--           UltraScale
-- Xilinx HDL Language Template, version 2023.1

BUFGCTRL_inst : BUFGCTRL
generic map (
   INIT_OUT => 0,                   -- Initial value of BUFGCTRL output, 0-1
   PRESELECT_I0 => FALSE,           -- BUFGCTRL output uses I0 input, FALSE, TRUE
   PRESELECT_I1 => FALSE,           -- BUFGCTRL output uses I1 input, FALSE, TRUE
   -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   IS_CE0_INVERTED => '0',          -- Optional inversion for CE0
   IS_CE1_INVERTED => '0',          -- Optional inversion for CE1
   IS_I0_INVERTED => '0',           -- Optional inversion for I0
   IS_I1_INVERTED => '0',           -- Optional inversion for I1
   IS_IGNORE0_INVERTED => '0',      -- Optional inversion for IGNORE0
   IS_IGNORE1_INVERTED => '0',      -- Optional inversion for IGNORE1
   IS_S0_INVERTED => '0',           -- Optional inversion for S0
   IS_S1_INVERTED => '0',           -- Optional inversion for S1
   SIM_DEVICE => "ULTRASCALE_PLUS"  -- ULTRASCALE, ULTRASCALE_PLUS
)
port map (
   O => O,             -- 1-bit output: Clock output
   CE0 => CE0,         -- 1-bit input: Clock enable input for I0
   CE1 => CE1,         -- 1-bit input: Clock enable input for I1
   I0 => I0,           -- 1-bit input: Primary clock
   I1 => I1,           -- 1-bit input: Secondary clock
   IGNORE0 => IGNORE0, -- 1-bit input: Clock ignore input for I0
   IGNORE1 => IGNORE1, -- 1-bit input: Clock ignore input for I1
   S0 => S0,           -- 1-bit input: Clock select for I0
   S1 => S1            -- 1-bit input: Clock select for I1
);

-- End of BUFGCTRL_inst instantiation

Verilog Instantiation Template


// BUFGCTRL: General Clock Control Buffer
//           UltraScale
// Xilinx HDL Language Template, version 2023.1

BUFGCTRL #(
   .INIT_OUT(0),                   // Initial value of BUFGCTRL output, 0-1
   .PRESELECT_I0("FALSE"),         // BUFGCTRL output uses I0 input, FALSE, TRUE
   .PRESELECT_I1("FALSE"),         // BUFGCTRL output uses I1 input, FALSE, TRUE
   // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   .IS_CE0_INVERTED(1'b0),         // Optional inversion for CE0
   .IS_CE1_INVERTED(1'b0),         // Optional inversion for CE1
   .IS_I0_INVERTED(1'b0),          // Optional inversion for I0
   .IS_I1_INVERTED(1'b0),          // Optional inversion for I1
   .IS_IGNORE0_INVERTED(1'b0),     // Optional inversion for IGNORE0
   .IS_IGNORE1_INVERTED(1'b0),     // Optional inversion for IGNORE1
   .IS_S0_INVERTED(1'b0),          // Optional inversion for S0
   .IS_S1_INVERTED(1'b0),          // Optional inversion for S1
   .SIM_DEVICE("ULTRASCALE_PLUS")  // ULTRASCALE, ULTRASCALE_PLUS
)
BUFGCTRL_inst (
   .O(O),             // 1-bit output: Clock output
   .CE0(CE0),         // 1-bit input: Clock enable input for I0
   .CE1(CE1),         // 1-bit input: Clock enable input for I1
   .I0(I0),           // 1-bit input: Primary clock
   .I1(I1),           // 1-bit input: Secondary clock
   .IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
   .IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
   .S0(S0),           // 1-bit input: Clock select for I0
   .S1(S1)            // 1-bit input: Clock select for I1
);

// End of BUFGCTRL_inst instantiation

Related Information

UltraScale Architecture Clocking Resources User Guide (UG572)