Use Cases - 2023.1 English - UG949

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-06-07
Version
2023.1 English

The typical cases for using the false path constraint are:

  • Ignoring timing on a path that is never active. For example, a path that crosses two multiplexers that can never let the data propagate in a same clock cycle because of the select pins connectivity.
    Figure 1. Path Cannot be Sensitized

    set_false_path -through [get_pins MUX0/I0] -through [get_pins MUX1/I1]
  • Ignoring timing on an asynchronous CDC path.
  • Ignoring static paths in the design. Some registers take a value once during the initialization phase of the application and never toggle again. When they appear to be on the critical path of the design, they can be ignored for timing to relax the constraints on the implementation tools and help with timing closure. It is sufficient to define a false path constraint from the static register only, without explicitly specifying the paths endpoints. For example, the paths from a 32-bit configuration register config_reg[31..0] to the rest of the design can be ignored by adding the following false path constraint:
    set_false_path -from [get_cells config_reg[*]]