Impact on Synthesis - 2023.1 English - UG949

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-06-07
Version
2023.1 English

The false path constraint is supported by synthesis and only impacts max delay (setup/recovery) path optimization. False path exceptions are recommended for portions of the design where timing can safely be ignored and for asynchronous CDC paths with no datapath delay requirements.