Parent runs are complete design images containing static logic and dynamic logic, for all reconfigurable modules in the design. The final routed design checkpoint can create a full device programming image plus one partial programming image per reconfigurable partition. This is the same capability as any parent or child run when using the standard DFX flow.
Child runs only contain the abstract shell plus the reconfigurable module implemented
within that shell, so routed designs only have the ability to generate partial
programming images for that reconfigurable module. A call to
write_bitstream or write_device_image must be done
using the -cell option to clearly request the partial image needed
(even though there is only one possible in that checkpoint).
If full design images with RMs implemented in child runs are desired, you must
first reassemble target configurations by linking full shell and reconfigurable module
routed checkpoints using open_checkpoint and read_checkpoint -cell, or add_files and link_design. Once
assembled, the current design in memory is a complete DFX design and a full bitstream
can be generated using a call to write_bitstream.