VCCAUX_IO - 2023.1 English - UG912

VCCAUX_IO specifies the operating voltage of the VCCAUX_IO rail for a given I/O. DRCs are available to ensure that VCCAUX_IO property assignments are correct:

• VCCAUXIOBT (warning): Ensures that ports with VCCAUX_IO values of NORMAL or HIGH are only placed in HP banks.
• VCCAUXIOSTD (warning): Ensures that ports with VCCAUX_IO values of NORMAL or HIGH do not use IOSTANDARDs that are only supported in HR banks.
• VCCAUXIO (error): Ensures that ports with VCCAUX_IO values of NORMAL are not constrained/placed in the same bank as a port with a VCCAUX_IO value of HIGH.

Architecture Support

7 series FPGAs and Zynq 7000 SoC devices on High Performance (HP) bank I/O only.

Applicable Objects

Ports (get_ports).

Value

• DONTCARE (default)
• NORMAL
• HIGH

Syntax

Verilog Syntax

To set this attribute, place the proper Verilog attribute syntax before the top-level output port declaration.

(* VCCAUXIO = "{DONTCARE|NORMAL|HIGH}" *)

Verilog Syntax Example:

// Specifies a “HIGH” voltage for the VCCAUX_IO rail connected to this I/O 
(* VCCAUX_IO = "HIGH" *) input ACT3,

VHDL Syntax

To set this attribute, place the proper VHDL attribute syntax before the top-level output port declaration.

Declare the VHDL attribute as follows:

attribute VCCAUX_IO : string;

Specify the VHDL attribute as follows:

attribute VCCAUX_IO of port_name : signal is value;

Where port_name is a top-level port.

VHDL Syntax Example:

ACT3 : in std_logic; 
attribute VCCAUX_IO : string;
-- Specifies a HIGH voltage for the VCCAUX_IO rail connected to this I/O 
attribute VCCAUX_IO of ACT3 : signal is “HIGH”;

XDC Syntax

set_property VCCAUX_IO value [get_ports port_name]

Where port_name is a top-level port.

XDC Syntax Example:

# Specifies a HIGH voltage for the VCCAUX_IO rail connected to this I/O 
set_property VCCAUX_IO HIGH [get_ports ACT3]

Affected Steps

• I/O Planning
• Place Design
• report_power