Dynamic Function eXchange (DFX) in AMD FPGAs and SoCs introduces new design requirements compared to traditional solutions. These requirements include unique approaches to source and runs management, as both bottom-up synthesis and multi-pass implementation are needed. These needs are met with the AMD Vivado™ Design Suite DFX Project Flow.
DFX flows can be run in project mode as illustrated in the following table for the two methodologies. Users must decide which path is best for their use case and needs, as the two flows cannot be mixed. One approach is an RTL-centric solution and the other is a block design-centric solution. Which flow is best for your needs? This chart compares differences between the two approaches:
| RTL Project Flow | IP integrator Project Flow | |
|---|---|---|
| Architecture Support | All architectures; not recommended for Versal | All architectures |
| Top Level design source | Verilog or VHDL | Block Design (with RTL wrapper) |
| Sources supported within RMs | IP, RTL, and EDIF | IP, BD, RTL, and EDIF |
| Designer Assistance, Connection Automation | No | Yes |
The same DFX Wizard and related design runs are used for both modes, and each uses a consistent set of design rule checks and safeguards. Ultimately, if you are targeting AMD Versal™ devices and/or need to include block design within RMs, the IP integrator flow is the choice for you. Otherwise, either approach is viable.