Using Vivado Debug Cores - 2023.1 English

Vivado tool debug cores (ILA, VIO, etc.) can be placed in any part of a Dynamic Function eXchange design, including within RMs. A specific design methodology is necessary to connect these cores to a central Debug Hub for communication throughout the device.

The connectivity between the central Debug Hub in static can be set up automatically, and this is triggered by a specific naming convention for the port names on the RP. These twelve pins are required, and the hub will be inferred if these exact names are used. Examples in Verilog, VHDL, and block design are below.

Following is the Verilog instantiation in the static design:

my_count counter_inst (
.clk(my_clk),
.dout(dout),
.S_BSCAN_drck(),
.S_BSCAN_shift(),
.S_BSCAN_tdi(),
.S_BSCAN_update(),
.S_BSCAN_sel(),
.S_BSCAN_tdo(),
.S_BSCAN_tms(),
.S_BSCAN_tck(),
.S_BSCAN_runtest(),
.S_BSCAN_reset(),
.S_BSCAN_capture(),
.S_BSCAN_bscanid_en()
);

Following is the VHDL component declaration and instantiation in the static design:

component my_count is
Port ( clk : in STD_LOGIC;
dout : out STD_LOGIC;
S_BSCAN_drck: IN std_logic := '0';
S_BSCAN_shift: IN std_logic := '0';
S_BSCAN_tdi: IN std_logic := '0';
S_BSCAN_update: IN std_logic := '0';
S_BSCAN_sel: IN std_logic := '0';  
S_BSCAN_tdo: OUT std_logic;
S_BSCAN_tms: IN std_logic := '0';
S_BSCAN_tck: IN std_logic := '0';
S_BSCAN_runtest: IN std_logic := '0';
S_BSCAN_reset: IN std_logic := '0';
S_BSCAN_capture: IN std_logic := '0';
S_BSCAN_bscanid_en: IN std_logic := '0'
);
end component;
…
counter_inst: my_count
port map (clk => my_clk,
dout => dout,
S_BSCAN_drck => open, 
S_BSCAN_shift => open, 
S_BSCAN_tdi => open, 
S_BSCAN_update => open, 
S_BSCAN_sel => open, 
S_BSCAN_tdo => open, 
S_BSCAN_tms => open, 
S_BSCAN_tck => open, 
S_BSCAN_runtest => open, 
S_BSCAN_reset => open, 
S_BSCAN_capture => open, 
S_BSCAN_bscanid_en => open
);

Within the RM top-level RTL, leave these twelve ports unconnected. Debug Hubs are inserted as black boxes, one in static and one in each RM during synthesis. These inserted IP are then expanded during opt_design. This is done for each RM, even if there are no debug cores within that RM (including greybox RMs).

If these exact port names cannot be used for any reason, such as the need to explicitly connect to multiple BSCAN instances, attributes can be used to drive the Debug Hub insertion. This approach must also be used if the first configuration processed does not have any debug cores present. Inference of Debug Hubs is not done if no debug cores within the RM can be found by the Vivado implementation tools.

In the syntax shown below, do not change anything other than the port names to assign Debug ports. These attributes are to be used in all RM top level source files.

Following are the Verilog attributes in the RM top level:

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN drck" *) (* DEBUG="true" *) 
input my_drck; 

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN shift" *) (* DEBUG="true" *) 
input my_shift;     

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tdi" *) (* DEBUG="true" *) 
input my_tdi;      

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN update" *) (* DEBUG="true" *)   
input my_update;     

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN sel" *) (* DEBUG="true" *)    
input my_sel;      

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tdo" *) (* DEBUG="true" *)    
output my_tdo;      

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tms" *) (* DEBUG="true" *)    
input my_tms;      

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN tck" *) (* DEBUG="true" *)    
input my_tck;      

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN runtest" *) (* DEBUG="true" *)  
input my_runtest;    

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN reset" *) (* DEBUG="true" *) 
input my_reset;     

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN capture" *) (* DEBUG="true" *)  
input my_capture;    

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN bscanid_en" *) 
(* DEBUG="true" *) input my_bscanid_en; 

Following are the VHDL attributes in the RM top level:

attribute X_INTERFACE_INFO : string; 

attribute DEBUG : string; 

attribute X_INTERFACE_INFO of my_drck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
drck"; 

attribute DEBUG of my_drck: signal is "true"; 

attribute X_INTERFACE_INFO of my_shift: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
shift"; 

attribute DEBUG of my_shift: signal is "true"; 

attribute X_INTERFACE_INFO of my_tdi: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
tdi"; 

attribute DEBUG of my_tdi: signal is "true"; 

attribute X_INTERFACE_INFO of my_update: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
update"; 

attribute DEBUG of my_update: signal is "true"; 

attribute X_INTERFACE_INFO of my_sel: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
sel"; 

attribute DEBUG of my_sel: signal is "true"; 

attribute X_INTERFACE_INFO of my_tdo: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
tdo"; 

attribute DEBUG of my_tdo: signal is "true"; 

attribute X_INTERFACE_INFO of my_tms: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
tms"; 

attribute DEBUG of my_tms: signal is "true"; 

attribute X_INTERFACE_INFO of my_tck: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
tck"; 

attribute DEBUG of my_tck: signal is "true"; 

attribute X_INTERFACE_INFO of my_runtest: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
runtest"; 

attribute DEBUG of my_runtest: signal is "true"; 

attribute X_INTERFACE_INFO of my_reset: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
reset"; 

attribute DEBUG of my_reset: signal is "true"; 

attribute X_INTERFACE_INFO of my_capture: signal is "xilinx.com:interface:bscan:1.0 S_BSCAN 
capture"; 

attribute DEBUG of my_capture: signal is "true"; 

attribute X_INTERFACE_INFO of my_bscanid_en: signal is "xilinx.com:interface:bscan:1.0 
S_BSCAN bscanid_en"; 

attribute DEBUG of my_bscanid_en: signal is "true"; 

You can use this approach for IP integrator as well. Use the following Tcl commands to add the necessary ports to a block design in an IP integrator flow:

create_bd_port -dir I S_BSCAN_drck
create_bd_port -dir O S_BSCAN_tdo
create_bd_port -dir I S_BSCAN_shift
create_bd_port -dir I S_BSCAN_tdi
create_bd_port -dir I S_BSCAN_update
create_bd_port -dir I S_BSCAN_sel
create_bd_port -dir I S_BSCAN_tms
create_bd_port -dir I S_BSCAN_tck
create_bd_port -dir I S_BSCAN_runtest
create_bd_port -dir I S_BSCAN_reset
create_bd_port -dir I S_BSCAN_capture
create_bd_port -dir I S_BSCAN_bscanid_en

The following figure shows the IP integrator canvas with the appropriate connectivity.

For an example of this core insertion as well as functionality within the Vivado Hardware Manager, see this link in Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947).