Tandem Configuration and Dynamic Function eXchange - 2023.1 English

UltraScale devices introduced the MCAP, a dedicated connection from one specific PCIe block on a device to the configuration engine, providing an efficient mechanism for delivering partial bitstreams. No explicit routes are required to connect the PCIe block to the configuration engine, saving considerable resources.

The MCAP is enabled by customizing an AMD PCIe IP with Dynamic Function eXchange or Tandem Configuration features. These features are available for three IP cores that support PCI Express:

• UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
• AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
• DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
• UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)

Tandem Configuration uses a two-stage methodology that enables the IP to meet the configuration time requirements indicated in the PCI Express Specification. The following use cases are supported with this technology:

Tandem PROM

Loads the single two-stage bitstream from the flash.

Tandem PCIe

Loads the first stage bitstream from flash, and deliver the second stage bitstream over the PCIe link to the MCAP.

Tandem with Field Updates

After a Tandem PROM (UltraScale only) or Tandem PCIe (UltraScale or UltraScale+) initial configuration, update the entire user design while the PCIe link remains active. The update region (floorplan) and design structure are pre-defined, and Tcl scripts are provided.

Tandem + Dynamic Function eXchange

This is a more general case of Tandem Configuration followed by Dynamic Function eXchange of any size or number of dynamic regions.

DFX over PCIe

This is a standard configuration followed by DFX, using the PCIe / MCAP as the delivery path of partial bitstreams.

The Tandem and DFX combined solutions have few additional requirements. This approach requires that the Pblocks for the HD.TANDEM_IP_PBLOCK and HD.RECONFIGURABLE parts of the design do not overlap. Otherwise, like a standard DFX design, any number or size RPs can be defined.

To enable any of these capabilities, select the appropriate option when customizing the core. In the Basic tab:

1. Change the Mode to Advanced.
2. Change the Tandem Configuration or Partial Reconfiguration option according to your desired case in UltraScale:
   • Tandem for Tandem PROM, Tandem PCIe or Tandem + Dynamic Function eXchange use cases
   • Tandem with Field Updates ONLY for the pre-defined Field Updates use case
   • DFX over PCIe to enable the MCAP link for Dynamic Function eXchange, without enabling Tandem Configuration
3. Change the Tandem Configuration or Partial Reconfiguration option according to your desired case in UltraScale+:
   • Tandem PROM for Tandem PROM or Tandem + Dynamic Function eXchange use cases
   • Tandem PCIe for Tandem PCIe or Tandem + Dynamic Function eXchange use cases
   • Tandem PCIe with Field Updates ONLY for the pre-defined Field Updates use case; Tandem PROM does not support Field Updates in UltraScale+
   • DFX over PCIe to enable the MCAP link for Dynamic Function eXchange, without enabling Tandem Configuration
     
     

The PCIe block that must be selected in most cases is the lowest instance in the device, except for SSI devices with three super logic regions (SLRs), in which case it is the lowest PCIe instance in the center SLR. A complete listing of the specific supported blocks is shown below in Table 1. All other PCIe blocks do not have the dedicated MCAP feature.

For complete information about Tandem Configuration, including required PCIe block locations, design flow examples, requirements, restrictions, flow details for Field Updates, and other considerations, see the Tandem Configuration section in UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) for UltraScale devices. For UltraScale+ devices, see UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

To easily find the package pin for the dedicated PCIe Reset for UltraScale devices, issue the following Tcl command:

get_package_pins -of_objects [get_sites IOB_X1Y103]

The MCAP is capable of operating at 200 MHz with a 32-bit data path. Traditionally bitstreams are loaded into the MCAP from a host PC through PCI Express configuration packets. In these systems the host PC and host PC software are the main factors which limit MCAP performance and bitstream throughput. Because PCIe performance of specific host PC and host PC software can vary widely, overall MCAP performance throughput might vary.

For more information and sample drivers, see Answer Record 64761.

If the performance of partial bitstream delivery using the MCAP port is insufficient, the ICAP can be used instead. While this approach does require additional logic to funnel configuration data from the PCIe end point to this internal configuration port, the ICAP can be saturated with 32-bit configuration data at the maximum clock rate (200 MHz for monolithic devices, 125 MHz for SSI devices). See Fast Partial Reconfiguration Over PCI Express Application Note (XAPP1338) for more information and an example design.