The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/24/2023 Version 2023.1 | |
| Adding Reconfigurable Modules with Sub-Module Netlists | Updated
link_design command. |
| Incremental Compile | Updated capabilities and limitations. |
| Nested DFX Design Considerations | Added information on limitations. |
| Abstract Shell for Dynamic Function eXchange | Added information on limitations. |
| Scoping Constraints to the Module Reference Block in the IP Integrator | Added section. |
| Export Hardware | Added information on hardware handoff. |
| Abstract Shell Creation and Usage | Clarified behavior of auto-generated runs for greyboxes. |
| Global Clocking Rules | Updated DFX behavior for different categories of clock nets. |
| Avoid Disjoint Pblocks Whenever Possible for UltraScale and UltraScale+ Devices | Added information on hd_visual scripts. |
| BLI Floorplan Alignment | Updated example and added special considerations for XPIO usage. |
| Floorplanning Design Rule Checks | Added section. |
| Known Restrictions for Clocking in Versal Device DFX Designs | Added information on clocking instances that might be prohibited due to expanded routing footprints. |
| Network on Chip | Added information on NoC instances within reconfigurable modules (RMs). |
| Static Routing Across SLR Boundaries | Updated example. |
| Adding Debug Cores for Versal Devices | Added section. |
| Range Only the Required Physical Sites within HSR Pblock Rectangles for Designs with Two RPs | Added new section. |
| Avoid Disjoint Pblocks Whenever Possible for Versal Devices | Added section. |
| Using Vivado Debug Cores | Added IP integrator Tcl commands. |
| Programming Image Compression | Updated syntax for disabling compression. |
| NoC Clock Gating Issue | Updated with information on Power Design Manager. |
| Supported Devices | Added devices. |
| Floorplanning DRC Examples | Added appendix. |