DFX designs for Versal devices have unique challenges related to ranging Pblocks in designs with two reconfigurable partitions (RPs). Due to the alignment of BLI tiles that are automatically ranged based on other ranged sites within an HSR clock region, the placement and routing footprints can extend farther than originally intended for a given Pblock rectangle. The extended footprints can lead to overlapping Pblock DRCs.
Therefore, it is recommended that you only range the sites required for
HSR Pblock rectangles. The following figures illustrate the differences. Originally, HSR
resources are added to a Pblock using the entire clock region designation. The green
highlighted sites outside of the pblock_rp0 Pblock are
automatically pulled into the placement footprint. You can view this using the hd_visual scripts. For example:
resize_pblock [get_pblocks pblock_rp0] -add {CLOCKREGION_X6Y0:CLOCKREGION_X6Y0}
In this example, an MMCM is present that only requires the MMCM and connected buffer sites. The I/Os within the design are constrained to static banks, so sites within the HSR clock region, such as IOB, XPHY, and XPIOLOGIC, are not needed. This Pblock can be adjusted to remove the full clock region range and only range necessary sites. For example:
resize_pblock [get_pblocks pblock_rp0] -remove {CLOCKREGION_X6Y0:CLOCKREGION_X6Y0}
resize_pblock [get_pblocks pblock_rp0] -add {BUFGCE_X6Y0:BUFGCE_X6Y23}
resize_pblock [get_pblocks pblock_rp0] -add {BUFGCTRL_X6Y0:BUFGCTRL_X6Y7}
resize_pblock [get_pblocks pblock_rp0] -add {MMCM_X6Y0:MMCM_X6Y0}The adjusted Pblock range has a much smaller placement footprint, which is highlighted in blue in the following figure. This reduced footprint can help to reduce the chances of overlapping with a second RP Pblock.
