HDPR-39 Reconfigurable Pblocks Must Not Lead to Overlap of Footprints in Same Frame Tile - 2023.1 English

Description

This DRC reports that a BLI tile is part of more than one reconfigurable Pblock, which is not supported in the DFX flow. This BLI tile gets pulled in by ranging tiles into a reconfigurable Pblock.

Example

The following DRC error can occur in DFX designs with two or more reconfigurable partitions (RPs). In this example, an AMD Versal™ device has two Pblocks: pblock_rp1rm1 and pblock_rp2rm1. Each RP has its own clock source in the HSR region.

HDPR-39#1 Error
Reconfigurable Pblocks must not lead to overlap of footprints in same frame tile  
Overlapping tile : BLI_LS_CORE_X30Y0 
	- Is in PLACEMENT footprint of reconfigurable pblock 'pblock_rp1rm1'
	  Footprint Expansion Path : 
		 - BLI_LS_CORE_X30Y0 tile in PLACEMENT footprint  for HSR_ROUTING
		 - CMT_MMCM_X14Y0 tile in PBLOCK
	- Is in PLACEMENT footprint of reconfigurable pblock 'pblock_rp2rm1' 
	  Footprint Expansion Path : 
		 - BLI_LS_CORE_X30Y0 tile in PLACEMENT footprint  for HSR_ROUTING
		 - XPIO_NIBBLE_SC_X29Y0 tile in PBLOCK
Resolution : Resize pblock to avoid overlaps in footprint using following tcl commands
	 * resize_pblock
	 * get_sites -of [get_tiles <tile in PBLOCK>]

Debugging

The Overlapping tile section of the DRC error lists the overlapping tile that is shared by two RPs: BLI_LS_CORE_X30Y0. The message suggests that HSR routing footprint led to the tile overlap. To show the routing footprint for both Pblocks, use the get_dfx_footprint command. For example:

highlight_objects -color yellow [get_dfx_footprint -place -of_objects [get_cells design_1_i/rp1rm1]]

mark_objects -color blue [get_dfx_footprint -place -of_objects [get_cells design_1_i/rp2rm1]]

In the following figure, the pblock_rp1rm1 routing footprint is highlighted in yellow, and the pblock_rp2rm1 routing footprint marked in blue. The tiles with both yellow highlights and blue marks indicate overlapping tiles.

The Footprint Expansion Path section of the DRC error shows how the overlapping tile BLI_LS_CORE_X30Y0 was included in pblock_rp1rm1. The CMT_MMCM_X14Y0 tile is part of the placement footprint of pblock_rp1rm1. Its PU includes the BLI tile that is overlapping. To show the routing footprint, use the get_dfx_footprint command. For example:

get_dfx_footprint -pu -of_objects [get_tiles CMT_MMCM_X14Y0 ]

This command returns BLI_LS_CORE_1_X29Y0, BLI_LS_CORE_X30Y0, and CMT_MMCM_X14Y0. Use the mark_objects command to show the overlapping tile in red.

mark_objects -color red [get_tiles BLI_LS_CORE_X30Y0 ]

The following figure shows the CMT_MMCM_X14Y0 tile in cyan and the overlapping BLI_LS_CORE_X30Y0 tile in red.

The PLACEMENT footprint section of the DRC error explains how the overlapping BLI tile is part of the pblock_rp2rm1. XPIO_NIBBLE_SC_X29Y0 is part of pblock_rp2rm1. Its PU includes the same overlapping BLI tile. To mark and select objects, you can use the following commands:

mark_objects -color orange [get_tiles XPIO_NIBBLE_SC_X29Y0 ]

select_objects [get_dfx_footprint -pu -of_objects [get_tiles XPIO_NIBBLE_SC_X29Y0 ]]

The following figure shows the Device view with XPIO_NIBBLE_SC_X29Y0 tile in orange and its PU selected.

Resolution

To resolve the violation, at least one Pblock must be resized. This is a design-dependent decision. In this example, one option is to remove resources from pblock_rp1rm1 that are unused from the HSR region, which can add additional connected, auto-inserted tiles. You can remove the overlapping tile, its corresponding frame, and its PUs from the second Pblock.

To determine the sites covered by the conflicting frame, you can enter the following commands:

get_sites -of_objects [get_dfx_footprint -pu -of_objects [get_dfx_footprint -frame -of_objects [get_tiles BLI_LS_CORE_X30Y0]]]

Using the sites returned from the get_sites command, find all necessary ranges corresponding to these sites that must be removed from the second Pblock as follows:

resize_pblock pblock_rp2rm1 -remove {IRI_QUAD_X59Y0:IRI_QUAD_X59Y15} -remove {IRI_QUAD_X58Y0:IRI_QUAD_X58Y15} -remove {XPIOLOGIC_X34Y0:XPIOLOGIC_X34Y2} -remove {IOB_X35Y0:IOB_X35Y2}

This example design had another HDPR-39 DRC error that identified BLI_DSP_ROCF_BL_TILE_X31Y0 as an overlapping tile. To remove the overlap, you can use the following command:

resize_pblock pblock_rp2rm1 -remove [get_sites -of_objects [get_dfx_footprint -pu -of_objects [get_dfx_footprint -frame -of_objects [get_tiles BLI_DSP_ROCF_BL_TILE_X31Y0]]]]

Some designs might error out due to a routing error caused by a required GND connection to a CMT site pin. To solve this routing issue, add the slice tile to the affected Pblock. A LUT tieoff resource must be present near the HSR region, which can be reached through the routing footprint. Use the report_route_status to provide a list of GND pins that were unrouted. For example:

Example: Nets with Routing Errors:
  		GLOBAL_LOGIC0
    	      Unrouted Pins -- only the first 10 are listed, use -show_all to get the full list:
      design_1_i/rp1rm1/clk_wizard_1/inst/clock_primitive_inst/DPLL_inst/DADDR[0]
      design_1_i/rp1rm1/clk_wizard_1/inst/clock_primitive_inst/DPLL_inst/DADDR[1]
      design_1_i/rp1rm1/clk_wizard_1/inst/clock_primitive_inst/DPLL_inst/DADDR[2]
      design_1_i/rp1rm1/clk_wizard_1/inst/clock_primitive_inst/DPLL_inst/DADDR[3]
      design_1_i/rp1rm1/clk_wizard_1/inst/clock_primitive_inst/DPLL_inst/DADDR[4]

This report route status shows that all unrouted nets originated from the same DPLL instance. You must choose the DPLL site and trace the connectivity (use the get_nodes command) until you find an interconnect tile. In the following figure, this is indicated by a red line.

Based on this example, the potential candidates are frames to the left or right of this gap between the Pblocks highlighted in purple, where the red line ends at the interconnect tile. If the left frame is chosen and the whole column is allocated to RP1, the placer might not work properly. Instead, remove the whole frame from RP2 as follows:

select_objects [get_dfx_footprint -pu -of_objects [get_dfx_footprint -frame -of_objects [get_tiles CLE_E_CORE_X30Y4]]]resize_pblock pblock_rp2rm1 -remove {SLICE_X88Y0:SLICE_X91Y91}

Allocate only one PU out of that frame to RP1 as follows:

resize_pblock pblock_rp1rm1 -add {SLICE_X88Y0:SLICE_X91Y0}

The following figure shows an example. RP2 is highlighted in green, and the DPLL site in RP1 is marked in yellow. The red line points at the selected SLICE (highlighted in yellow) that is added to RP1 to enable the router to route the VCC/GND net.