Floorplanning for Versal Devices - 2023.1 English

Floorplanning for Versal Devices - 2023.1 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID

UG909

Release Date

2023-05-24

Version

2023.1 English

As part of improvements to the Versal architecture, the smallest unit that can be reconfigured is much smaller than in previous architectures. The minimum required resources for reconfiguration varies based on the resource type, and are referred to as a Programmable Unit (PU). Many site types have improved PU requirement making granularity of reconfigurable Pblocks significantly improved compared to previous architecture.

Tip: While the fundamental building blocks are shown in the following images, in real design scenarios they will be part of a larger collection of resources, creating a comprehensive floorplan for each dynamic region.

Following are the details provided for each site type.

Programmable Logic (PL) NoC NMU and NSU: The PU is the corresponding NOC_NMU or NOC_NSU tile.
Figure 1. PL NoC NMU and NSU
CLE: Two adjacent CLE tiles share a routing resource (interconnect tile). The PU is the two CLE tiles (four SLICE sites) with shared interconnect.
Figure 2. CLE PU
BRAM: The PU is the corresponding BRAM tile. One BRAM tile includes two RAMB18s and one RAMB36. Adjacent INTF and INT tiles are automatically pulled into the routing footprint if it is not covered by the Pblock. Unlike previous architecture, adjacent CLE sites are not part of the BRAM PU.
Figure 3. BRAM PU: RAMB18s and RAMB36 of One BRAM Tile
URAM: The PU is the corresponding URAM tile. One URAM tile includes only one URAM site. The adjacent INTF and INT tiles are automatically pulled into the routing footprint if it is not covered by the Pblock.
Figure 4. URAM PU: URAM Tile
DSP: The PU is the corresponding DSP tile. One DSP tile includes two DSP sites.
Figure 5. DSP PU: DSP Tile
IRI_QUAD (ODD/EVEN): The PU is the corresponding INTF_ROCF_TL_TILE. One tile includes four IRI Quads. The INTF at the center of the IRI quads is automatically pulled into the routing footprint. Although IRI_QUADs are user range-able, the adjacent IRI_QUADs of the RP Pblock are automatically pulled into the routing footprint, because the expanded routing footprint is always a two INT tile expansion.
Figure 6. IMUX Register Interface Quad: PU is INT_ROCF_TL Tile
PCIe: The PU is the corresponding PCIEB_BOT_TILE. The adjacent INTF tiles are automatically included in the routing footprint of the reconfigurable Pblock.
Figure 7. PCIe PU is PCIe Tile
GTY_QUAD: The PU is the corresponding GTY_QUAD_SINGLE tile. Sites included in the tile are GTY_QUAD and GTY_REFCLK. The adjacent INTF_GT tiles are automatically pulled into the routing footprint of the reconfigurable Pblock.
Figure 8. GTY_QUAD PU is GTY_QUAD Tile
DDRMC and DDRMC_RUI: The PUs are the corresponding DDRMC_DMC_CORE and DDRMC_RIU_CORE tiles respectively.
Figure 9. DDMRC PU

Figure 10. DDMRC_RUI PU
MMCM: The PU is a corresponding CMT_MMCM tile.
Figure 11. MMCM PU is CMT_MMCM Tile
XPLL: The PU is the corresponding CMT_XPLL tile.
Figure 12. XPLL PU is CMT_XPLL Tile
DPLL: The PU is the corresponding CMT_DPLL tile.
Figure 13. DPLL PU is CMT_DPLL Tile
MRMAC: The PU is the corresponding MRMAC_BOT tile.
Figure 14. MRMAC PU is MRMAC_BOT Tile
BUFG_FABRIC, BUFG_PS and GCLK_DELAY: These three site types are included in same CLK_VNOC tile. BUFG_PS will be present only in the VNOC column adjacent to CIPS. Other VNOC tiles include only BUFG_FABRIC and GCLK_DELAY. The PU requirement is the CLK_VNOC tile.
Figure 15. BUFG_FABRIC, BUFG_PS, and GCLK_DELAY Shares Same Tile As PU
XPHY, XPIO and IOB: An I/O bank in Versal devices cannot be shared by static and reconfigurable partitions. All XPIO_NIBBLE tiles of one I/O bank must be used by one partition only.
BUFG_GT, BUFG_GT_SYNC and GCLK_DELAY: The CLK_GT tile is the PU.
Figure 16. BUFG_GT, BUFG_GT_SYNC Share Same PU: CLK_GT Tile
XPIPE_QUAD: The XPIPE_QUAD tile is the PU.
Figure 17. XPIPE_QUAD PU
BUFGCE, BUFGCTRL, and BUFGCE_DIV: For the BUFGCE elements in HSR, the PU is the CLK_REBUF_BUFGS_HSR_CORE tile.
Figure 18. Clocking Buffers in HSR Has CLK_REBUF_BUFG_HSR_CORE Tile As PU
BUFGCE_HDIO, HDIO_BIAS, HDIO_LOGIC, and IOB: For these sites in HDIO, the PU is the HDIO_TILE tile.
Figure 19. Clock Buffers and IOB in HDIO Bank Share Same PU: HDIO_TILE