Configuration Modes - 2023.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
Document ID
UG909
Release Date
2023-05-24
Version
2023.1 English

Dynamic Function eXchange is supported using the following configuration modes:

ICAP
A good choice for user configuration solutions. Requires the creation of an ICAP controller as well as logic to drive the ICAP interface.
MCAP
(AMD UltraScale™ ™ and AMD UltraScale+™ ™ devices only) Provides a dedicated connection to the configuration engine from one specific PCIe® block per device.
PCAP
The primary configuration mechanism for AMD Zynq™ 7000 SoC and Zynq UltraScale+ MPSoC™ designs.
JTAG
A good interface for quick testing or debug. Can be driven with the AMD Vivado™ Logic Analyzer.
Slave SelectMAP or Slave Serial
A good choice to perform full configuration and dynamic reconfiguration over the same interface.

Master modes are not directly supported because IPROG housecleaning clears the configuration memory.

Table 1. Supported Configuration Ports
Configuration Mode 7 series Zynq UltraScale UltraScale+ Zynq UltraScale+ MPSoC
JTAG 2 Yes Yes Yes Yes Yes
ICAP Yes Yes Yes Yes Yes
PCAP N/A Yes N/A N/A Yes
MCAP N/A N/A Yes Yes Yes
Slave Serial Yes N/A Yes Yes N/A
Slave SelectMap Yes N/A Yes Yes N/A
SPI (any width) 1 No N/A No Yes N/A
BPI sync mode No N/A No Yes N/A
BPI async mode Yes N/A Yes Yes N/A
Master modes No N/A No No N/A
  1. SPI and BPI flash can be used to store partial bitstreams, but the STARTUP primitive cannot be used to deliver partial bitstreams to the configuration engine for devices prior to UltraScale+. The static design would need to be connected to the flash via user IO, and a controller would be used to fetch bitstreams for delivery to the ICAP.
  2. JTAG mode is always available independent of the Mode pin settings. Setting the Mode pins to JTAG-only (M[2:0]=101) is not recommended, as this disrupts partial bitstream delivery to other configuration ports, including ICAP.

To use external configuration modes (other than JTAG) for loading a partial BIT file, these pins must be reserved for use after the initial device configuration. This is achieved by using the BITSTREAM.CONFIG.PERSIST property to keep the dual-purpose I/O for configuration usage and to set the configuration width. Refer to this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908). The Tcl command syntax to set this property is:

set_property BITSTREAM.CONFIG.PERSIST <value> [current_design]

where <value> is either No or Yes.

Note: When configuration pins are persisted, the ICAP is disabled; the two features are mutually exclusive. For more information on the ICAP, see 7 Series FPGAs Configuration User Guide (UG470) or UltraScale Architecture Configuration User Guide (UG570), depending on your device.

Partial bitstreams contain all the configuration commands and data necessary for Dynamic Function eXchange. The task of loading a partial bitstream into an FPGA does not require knowledge of the physical location of the RM because configuration frame addressing information is included in the partial bitstream. A valid partial bitstream cannot be sent to the wrong part of the FPGA.

A DFX controller retrieves the partial bitstream from memory, then delivers it to a configuration port. The DFX control logic can either reside in an external device (for example, a processor) or in the programmable logic of the FPGA to be reconfigured. A user-designed internal DFX controller loads partial bitstreams through the ICAP interface. As with any other logic in the static design, the internal DFX control circuitry operates without interruption throughout the reconfiguration process.

Internal configuration can consist of either a custom state machine, or an embedded processor such as MicroBlaze. For a Zynq 7000 SoC and Zynq UltraScale+ MPSoC, the Processor Subsystem (PS) can be used to manage partial reconfiguration events.

Note: For Zynq 7000 SoC devices, the Programmable Logic (PL) can be partially reconfigured, but the Processing System cannot.

As an aid in debugging Dynamic Function eXchange designs and DFX control logic, the Vivado Logic Analyzer can be used to load full and partial bitstreams into an FPGA by means of the JTAG port.

For more information on loading a bitstream into the configuration ports, see the Configuration Interfaces chapter in these documents:

  • 7 Series FPGAs Configuration User Guide (UG470)
  • UltraScale Architecture Configuration User Guide (UG570)
  • Zynq-7000 SoC Technical Reference Manual (UG585)