Zynq UltraScale+ MPSoC Bitstream Settings - 2023.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.1 English

The device configuration settings for AMD Zynq™ UltraScale+™ MPSoC devices available for use with the set_property <Setting> <Value> [current_design] Vivado tool Tcl command are shown in the following table.

Table 1. Zynq UltraScale+ MPSoC Bitstream Settings
Setting Default Values Possible Value Description
BITSTREAM.CONFIG. DCIUPDATEMODE AsRequired AsRequired, Quiet, Safe Controls how often the Digitally Controlled Impedance circuit attempts to update the impedance match for DCI IOSTANDARDs.
BITSTREAM.CONFIG. PUDC_B Pullup Pullup, Pulldown, Pullnone Adds an internal pull-up, pull-down, or neither to the PUDC_B pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the PUDC_B pin.
BITSTREAM.CONFIG. OVERTEMPSHUTDOWN Disable Disable, Enable Enables the device to shut down when the System Monitor detects a temperature beyond the acceptable operational maximum. An external circuitry set up for the System Monitor is required to use this option.
BITSTREAM.CONFIG. UNUSEDPIN Pulldown Pullup, Pulldown, Pullnone Adds a pull-up, a pull-down, or neither to unused SelectIO pins (IOBs). It has no effect on dedicated configuration pins. The list of dedicated configuration pins varies depending upon the architecture. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.
BITSTREAM.CONFIG. USERID 0xFFFFFFFF 0xFFFFFFFF Used to identify implementation revisions. You can enter up to an 8-digit hexadecimal string in the User ID register.
BITSTREAM.CONFIG. USR_ACCESS None None, <8-digit hex string>, TIMESTAMP Writes an 8-digit hexadecimal string, or a timestamp into the AXSS configuration register. The format of the timestamp value is ddddd MMMM yyyyyy hhhhh mmmmmm ssssss : day, month, year (year 2000 = 00000), hour, minute, seconds. The contents of this register can be directly accessed by the FPGA fabric via the USR_ACCESS primitive.
BITSTREAM.CONFIG. INITSIGNALSERROR Enable Enable, Disable When Enabled, the INIT_B pin asserts to '0' when a configuration error is detected.
BITSTREAM.GENERAL. COMPRESS False True, False Uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not the bit file. Using compress does not guarantee that the size of the bitstream shrinks.
BITSTREAM.GENERAL. CRC Enable Enable, Disable Controls the generation of a Cyclic Redundancy Check (CRC) value in the bitstream. When enabled, a unique CRC value is calculated based on bitstream contents. If the calculated CRC value does not match the CRC value in the bitstream, the device fails to configure. When CRC is disabled a constant value is inserted in the bitstream in place of the CRC, and the device does not calculate a CRC.
BITSTREAM.GENERAL. PERFRAMECRC No No, Yes Inserts CRC values at regular intervals within bitstreams. These values validate the integrity of the incoming bitstream and can flag an error (shown on the INIT_B pin and the PRERROR port of the ICAP) prior to loading the configuration data into the device. While most appropriate for partial bitstreams, when set to Yes, this property inserts the CRC values into all bitstreams, including full device bitstreams.
BITSTREAM.GENERAL. SYSMONPOWERDOWN Disable Disable, Enable Enables the device to power down SYSMON to save power. Only recommended for permanently powering down SYSMON.
BITSTREAM.GENERAL. DISABLE_JTAG No No, Yes Disables communication to the Boundary Scan (BSCAN) block via JTAG after configuration.
BITSTREAM.GENERAL. JTAG_SYSMON Enable Enable, Disable, StatusOnly Enables or disables the JTAG connection to SYSMON.
BITSTREAM.READBACK. ICAP_SELECT Auto Auto, Top, Bottom Selects between the top and bottom ICAP ports.
BITSTREAM.READBACK. ACTIVERECONFIG No No, Yes Prevents the assertions of GHIGH and GSR during configuration. This is required for the active partial reconfiguration enhancement features.

Specifies whether to disable Readback and Reconfiguration.

Specifying Security Level1 disables Readback.Specifying Security

BITSTREAM.STARTUP. DONE_CYCLE 4 4, 1, 2, 3, 5, 6, Keep Selects the Startup phase that activates the FPGA Done signal. Done is delayed when DonePipe=Yes
BITSTREAM.STARTUP. GTS_CYCLE 5 5, 1, 2, 3, 4, 6, Done, Keep Selects the Startup phase that releases the internal 3-state control to the I/O buffers
BITSTREAM.STARTUP. GWE_CYCLE 6 6, 1, 2, 3, 4, 5, Done, Keep Selects the Startup phase that asserts the internal write enable to flip-flops, LUT RAMs, and shift registers. GWE_cycle also enables the BRAMS. Before the Startup phase, both block RAMs writing and reading are disabled.
BITSTREAM.STARTUP. LCK_CYCLE NoWait NoWait, 0, 1, 2, 3, 4, 5, 6 Selects the Startup phase to wait until MMCM/PLLs lock. If you select NoWait, the Startup sequence does not wait for MMCM/PLLs to lock.
BITSTREAM.STARTUP. MATCH_CYCLE Auto Auto, NoWait, 0, 1, 2, 3, 4, 5, 6

Specifies a stall in the Startup cycle until digitally controlled impedance (DCI) match signals are asserted. DCI matching does not begin on the Match_cycle. The Startup sequence waits in this cycle until DCI has matched. Given that there are a number of variables in determining how long it takes DCI to match, the number of CCLK cycles required to complete the Startup sequence can vary in any given system. Ideally, the configuration solution should continue driving CCLK until DONE goes high.

When the Auto setting is specified, write_bitstream searches the design for any DCI I/O standards. If DCI standards exist, write_bitstream uses BITSTREAM.STARTUP.MATCH_CYCLE=2. Otherwise, write_bitstream uses BITSTREAM.STARTUP.MATCH_CYCLE=NoWait.