The output probes of a VIO core can become out-of-sync with the Vivado IDE after resetting the VIO outputs, re-programming the FPGA or adaptive SoC, or by another Vivado tool instance setting output values before the current instance has started. In any case, if the VIO status indicates "Outputs out-of-sync", you need to take one of two actions:
- Write the values from the Vivado IDE to the
VIO core by right-clicking the VIO core in the Hardware window and selecting the
Commit VIO Core Outputs option. You can
also do this by running a Tcl command:
commit_hw_vio [get_hw_vios {hw_vio_1}] - Update the Vivado IDE with the current values
of the VIO core output probe ports by right-clicking the VIO core in the Hardware
window and selecting the Refresh Input and Output Values
from VIO Core option. You can also do this by running a Tcl command:
refresh_hw_vio -update_output_values 1 [get_hw_vios {hw_vio_1}]