The HDL instantiation probing flow involves the manual customization, instantiation, and connection of various debug core components directly in the HDL design source. The new debug cores that are supported in this flow in the Vivado tool are shown in table the following table.
| Debug Core | Version | Description | Runtime Analyzer Tool |
|---|---|---|---|
| ILA (Integrated Logic Analyzer) | v6.2 | Debug core that is used to trigger on hardware events and capture data at system speeds. | Vivado logic analyzer |
| VIO (Virtual Input/Output) | v3.0 | Debug core that is used to monitor or control signals in design at JTAG chain scan rates. | Vivado logic analyzer |
| JTAG-to-AXI Master | v1.2 | Debug core that is used to generate AXI transactions to interact with various AXI full and AXI lite slave cores in a system that is running in hardware. | Vivado logic analyzer |
The new ILA core has two distinct advantages over the legacy ILA v1.x core:
- Works with the integrated Vivado logic analyzer feature (refer to Debugging Logic Designs in Hardware).
- No ICON core instance or connection is required.