Table Columns - 2023.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2023-05-16
Version
2023.1 English

The table columns are:

ID
A numeric ID for the source/destination clock pair being displayed.
Source Clock
The clock domain from which the path originates.
Destination Clock
The clock domain within which the path terminates.
Edges (WNS)
The clock edges used to calculate the worst negative slack for max delay analysis (setup/recovery).
WNS (Worst Negative Slack)
The worst slack calculated for various paths crossing the specified clock domains. A negative slack indicates a problem in which the path violates a required setup (or recovery) time.
Total Negative Slack
The sum of the worst slack violation for all the endpoints that belong to paths crossing the specified clock domains.
Failing Endpoints
The number of endpoints in the crossing paths that fail to meet timing. The sum of the violations corresponds to TNS.
Total Endpoints (TNS)
The total number of endpoints in the crossing paths.
Path Req (WNS)
The timing path requirement corresponding to the path reported in the WNS column. There can be several path requirements between any clock pairs if both rising and falling edges are active for at least one of the two clocks, or some timing exceptions have been applied on paths between the two clocks. The value reported in this column is not always the most challenging requirement.

For more information, see Path Requirement.

Clock Pair Classification
Provides information about the common node and common period between the clock pair. From highest to lowest precedence: Ignored, Virtual Clock, No Common Clock, No Common Period, Partial Common Node, No Common Node, No Common Phase, and Clean. See Clock Pair Classification.
Inter-Clock Constraints
Shows the constraints summary for all paths between the source clock and destination clock. The possible values are listed in the Matrix Color Coding. Following are example definitions of these constraints:
set_clock_groups -async -group wbClk -group usbClk
set_false_path -from [get_clocks wbClk] -to [get_clocks cpuClk]

When the min delay analysis is also selected (hold/removal), the following columns also appear in the table:

Edges (WHS)
The clock edges used to calculate the worst hold slack.
WHS (Worst Hold Slack)
The worst slack calculated for various paths crossing the specified clock domains. A negative slack indicates a problem in which the path violates a required hold (or removal) time.
THS (Total negative Hold Slack):
The sum of the worst slack violation for all the endpoints that belong to paths crossing the specified clock domains for min delay analysis (hold/removal).
Failing Endpoints (THS)
The number of endpoints in the crossing paths that fail to meet timing. The sum of the violations corresponds to THS.
Total Endpoints (THS)
The total number of endpoints in the crossing paths for min delay analysis (hold/removal).
Path Req (WHS)
The timing path requirement corresponding to the path reported in the WHS column. Like with WNS, there can be several possible path requirements for min delay analysis between two clocks, and the value reported in this column does not always correspond to the most challenging ones.

For more information, see Timing Analysis.

One or multiple clock pairs can be selected from the table. Report Timing between a selected source/destination clock pair can be run from the popup menu.