The solution is to add the ASYNC_REG constraint to each stage of the logic
synchronizer. For a detailed list of CDC violations, run report_cdc. To find out more information on the ASYNC_REG
constraint, refer to the
Vivado
Design Suite Properties Reference Guide (UG912). The
TIMING-10 violation is triggered when at least one of the first two synchronizer
registers is missing the ASYNC_REG property.