Example - 2023.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2023-05-16
Version
2023.1 English

In the following figure, an asynchronous clock domain exists between clk1 and clk2. However, the clk2 capture domain does not contain a double register logic synchronizer to synchronize the data.

Figure 1. Missing Synchronizer
Page-1 Process Missing double register logic synchronizer on the capture dom... Missing double register logic synchronizer on the capture domain Sheet.2 Sheet.3 Process.11 Process.8 Clock domain crossing Clock domain crossing Sheet.6 Sheet.8 X15528-111715 X15528-111715