In the following example, a user has written a counter as follows:
The signal cnt counts from 0 to 16, which requires
a 5-bit vector to encode. The post-route critical schematics is shown in the following
figure. The endpoint is the bit 30 of the cnt
signal.
After selecting the startpoint and endpoint cells of the critical path, you can visualize the equivalent path in the elaborated view by opening a schematics of the selected cells and expanding the logic from the endpoint pin back to the startpoint, as shown in the following figure.
The elaborated view shows that the adder-input has been sized to 32 bit, because the signal cnt is declared as an integer. In this particular example, the 32-bit operator is retained throughout the synthesis optimizations. The elaborated view gives a good hint of what is happening and you can change the RTL as follows in order to get a better optimized netlist and timing QoR. As the counter increments from 0 to 16, you can define a range for the signal cnt which forces the adder-inputs to be 5 bits wide instead of 32 bits wide.
The change made to the RTL code will subsequently impact the synthesis optimization, which you can verify using the elaborated view instead of going through the entire compilation flow: