Description - 2023.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2023-05-16
Version
2023.1 English

The DRC warning only occurs when a set_max_delay -datapath_only constraint is overridden by a set_clock_groups or set_false_path constraint between clocks. If a point-to-point set_false_path constraint overrides a set_max_delay -datapath_only constraint, the DRC will not be reported.