This check applies to Versal adaptive SoC only.
In Versal adaptive SoC devices, it is only
safe to time between the DPLL input clock and one of its output clocks when the phase
detector (CLKOUTx_PHASE_CTRL=01) is used and the CLKIN_DESKEW pin is connected to the CLKIN pin. In all other cases, the phase relationship between the master
clock and the auto-derived clocks is unknown and the clock domain crossing between them
should be considered asynchronous: any path in the crossing should have the proper
synchronization circuitry in the destination clock domain.