Clock Pair Classification - 2023.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2023-05-16
Version
2023.1 English

The Clock Pair Classification column provides information about the missing common primary clock, missing common node, missing common phase, and missing common period between two clocks, as well as the presence of a virtual clock.

The possible values, from the highest to the lowest priority, are listed below. As soon as a condition is detected, the report command does not perform the remaining checks.

Ignored
When the clock pair is entirely covered by a clock group, a false path, or a max delay datapath only, the analysis is ignored.
Note: When a clock pair is covered by a max delay datapath only, the Inter-Clock Constraints are reported as Max Delay Datapath Only during setup analysis and as Auto Generated False Path during hold analysis (-delay_type min).
Virtual Clock
At least one of the clocks is virtual, and common primary clock or common node checks do not apply.
No Common Clock
The two clocks do not have a common primary clock.
No Common Period
The periods of the two clocks are not expandable.
Partial Common Node
The two clocks appear synchronous, but a subset of the crossing paths does not have a common node and cannot be safely timed.
No Common Node
The two clocks appear synchronous, but the crossing paths do not have a common node.
No Common Phase
The two clocks do not have a known phase relationship.
Clean
None of the above conditions applies.