Verilog Primitives - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

Vivado synthesis supports Verilog gate-level primitives except as shown in the following table.

Vivado synthesis does not support Verilog switch-level primitives, such as the following:

cmos, nmos, pmos, rcmos, rnmos, rpmos rtran, rtranif0, rtranif1, tran, tranif0, tranif1