Verilog Parameters - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2023.1 English

Verilog parameters do the following:

  • Allow you to create parameterized code that can be easily reused and scaled.
  • Make code more readable, more compact, and easier to maintain.
  • Describe such functionality as:
    • Bus sizes
    • The amount of certain repetitive elements in the modeled design unit
  • Are constants. For each instantiation of a parameterized module, default operator values can be overridden.
  • Are the equivalent of VHDL generics. Null string parameters are not supported.

Use the Generics command line option to redefine Verilog parameters defined in the top-level design block. This allows you to modify the design without modifying the source code. This feature is useful for IP core generation and flow testing.