Verilog Meta Comments - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2023.1 English
  • Verilog meta comments are understood by the Verilog parser.
  • Verilog meta comments set constraints on individual objects, such as:
    • Module
    • Instance
    • Net
  • Verilog meta comments set directives on synthesis:
    • parallel_case and full_case
    • translate_on and translate_off
    • All tool specific directives (for example, syn_sharing)