Verilog defines macros as follows:
'define TESTEQ1 4'b1101
The defined macro is referenced later, as follows:
if (request == 'TESTEQ1)
The 'ifdef
and 'endif
constructs do the following:
- Determine whether a macro is defined.
- Define conditional compilation.
If the macro called out by 'ifdef
is defined, that code is compiled.
- If the macro has not been defined, the code following the
'else
command is compiled. - The
'else
is not required, but'endif
must complete the conditional statement.
Use the Verilog Macros command line option to define (or redefine) Verilog macros.
- Verilog Macros let you modify the design without modifying the HDL source code.
- Verilog Macros is useful for IP core generation and flow testing.