VHDL in Verilog - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

Vivado synthesis has the following limitations when instantiating a VHDL design unit in a Verilog module:

  • The only VHDL construct that can be instantiated in a Verilog design is a VHDL entity. No other VHDL constructs are visible to Verilog code. Vivado synthesis uses the entity-architecture pair as the Verilog-VHDL boundary.
  • Use explicit port association. Specify formal and effective port names in the port map.
  • All parameters are passed at instantiation, even if they are unchanged.
  • The override is named and not ordered. The parameter override occurs through instantiation, not through defpas.