VHDL Sequential Processes Without a Sensitivity List - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

Vivado synthesis allows the description of a sequential process using a wait statement. The sequential process is described without a sensitivity list.

The wait statement is the first statement and the condition in the wait statement describes the sequential logic clock.

Important: The same sequential process cannot have both a sensitivity list and a wait statement, and only one wait statement is allowed.