A VHDL process is sequential (as opposed to combinatorial) when some assigned signals are not explicitly assigned in all paths within the process. The generated hardware has an internal state or memory (Flip-Flops or Latches).
Recommended: Use a sensitivity-list based description
style to describe sequential logic.
Describing sequential logic using a process with a sensitivity list includes:
- The clock signal
- Any optional signal controlling the sequential element asynchronously (asynchronous set/reset)
- An if statement that models the clock event.