Vivado synthesis supports the following predefined VHDL
enumerated types.
Table 1. VHDL Enumerated Type Summary
| Enumerated Type |
Defined In |
Allowed Values |
| bit |
standard package |
- 0 (logic zero)
- 1 (logic 1)
|
| boolean |
standard package |
|
| std_logic |
IEEE std_logic_1164 package |
See std_logic Allowed Values. |
std_logic Allowed Values
Table 2. std_logic Allowed Values
| Value |
Meaning |
What Vivado synthesis does |
| U |
initialized |
Not accepted by Vivado synthesis |
| X |
unknown |
Treated as do not care |
| 0 |
low |
Treated as logic zero. |
| 1 |
high |
Treated as logic one |
| Z |
high impedance |
Treated as high impedance |
| W |
weak unknown |
Not accepted by Vivado synthesis |
| L |
weak low |
Treated identically to 0 |
| H |
weak high |
Treated identically to 1 |
| - |
don’t care |
Treated as do not care |