VHDL Assert Statements - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2023.1 English

Assert statements are supported with the -assert synthesis option.

Care should be taken using asserts. Vivado can only support static asserts that do not create or are created by behavior. For example, performing as assert on a value of a constant or an operator/generic works; however, as an asset on the value of a signal inside an if statement does not work.