VHDL Architecture Declaration Coding Example - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English
library IEEE;
use IEEE.std_logic_1164.all;

entity EXAMPLE is
port (
A,B,C : in std_logic;
D,E : out std_logic );
end EXAMPLE;

architecture ARCHI of EXAMPLE is
signal T : std_logic;
begin
...
end ARCHI;