Using case? Statements - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2023.1 English

With VHDL-2008, the case statement has a way to deal with explicit don’t care assignments. When using case? , the tool now evaluates explicit don’t care terms, as in the following example:

process(clk) begin
if clk'event and clk='1' then
case? my_reg is
when "01--" => out1 <= in1;
when "000-" => out1 <= in2;
when "1111" => out1 <= in3;
when others => out1 <= in4;
end case?;
end if;
end process;
Note: For this statement to work, the signal in question must be assigned an explicit don’t care.