Using While Loops - 2023.1 English

When using always blocks, use while loops to execute repetitive procedures.

• A while loop:
  • Is not executed if the test expression is initially false.
  • Executes other statements until its test expression becomes false.
• The test expression is any valid Verilog expression.
• To prevent endless loops, use the -loop_iteration_limit option.
• A while loop can have disable statements. The disable statement is used inside a labeled block, as shown in the following code snippet:

disable <blockname>